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分享 [Hspice] switch between two voltage sources connected to the same node
wildgoat 2013-8-23 15:41
Question: How can I switch between two voltage source connected to the same node for some time and duration using HSPICE elements. Answer: There are two ways to do this. One is to design a Verilog-A module that can be used as a behavioral switch. Another is to use the HSPICE voltage cont ...
个人分类: Hspice|1454 次阅读|0 个评论
分享 [Hspice] Source with jitter
wildgoat 2013-8-23 15:34
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Question: Is there a test bench showing how to add jitter to the PRBS source? Answer: The attached example contains a sample and hold Verilog-A model which can be used to add jitter to a PRBS source. Care should be taken so that ...
个人分类: Hspice|11406 次阅读|0 个评论
分享 [Hspice] Verilog-A Model Encryption
wildgoat 2013-8-23 15:27
———————————————————————————————— Question: Does HSPICE support encryption of Verilog-A modules? Answer: Beginning with the E-2010.12-SP2 release, HSPICE can encrypt Verilog-A modules. The two methods supported are: 1) 8-Byte encryption 2) 3DES encrypt ...
个人分类: Hspice|3656 次阅读|0 个评论
分享 [Hspice] Printing Non-electrical Variables in Verilog-A to the Waveform File
wildgoat 2013-8-23 13:27
Question: How can I dump the values of non-electrical Verilog-A variables to the waveform. file? Answer: 1. Set the environment variable HSP_VACOMP_OPTIONS -G at the command prompt (on UNIX/Linux). % setenv HSP_VACOMP_OPTIONS -G 2. Add a .PROBE statement to the top level SPICE netli ...
个人分类: Hspice|5009 次阅读|0 个评论
分享 XP下Hspice_D-2010.03-SP1无法运行的一个例子
wildgoat 2011-12-15 23:31
Normal 0 false false false EN-US ZH-CN X-NONE
个人分类: Hspice|4180 次阅读|7 个评论
分享 Matlab中调用Hspice
wildgoat 2011-9-11 02:15
! D:\EDA\synopsys\Hspice_D-2010.03-SP1\BIN\hspice amplifier.sp amplifier D:\EDA\synopsys\Hspice_D-2010.03-SP1\BIN\hspice -i amplifier.sp -o amplifier D:\EDA\synopsys\Hspice_D-2010.03-SP1\BIN\hspice -i amplifier.sp 注意: 1. 如果网表文件amplifier.sp ...
个人分类: Hspice|5724 次阅读|0 个评论
分享 .PRINT, .PLOT及.PROBE等的区别
wildgoat 2011-8-6 02:48
1. .print will store the simulation output in a special file(*.tr#,*.ac#, etc) for following analysis by waveform. viewer.At the same time, itprints the value in text format (in the ".lis file) for you, so you can checkout the text output format. .probe only store the simu ...
个人分类: Hspice|11979 次阅读|0 个评论
分享 用Cadence与hspice配合仿真模拟电路(转)
wildgoat 2011-1-15 02:00
Cadence 公司有全套的 模拟电路 设计 软件 ,但是实际情况多数设计公司都是使用Cadence与Synopsys两家公司的部分软件结合使用,各取所长。使用Cadence套件 输入 电原理图,然后使用Synopsys的 Hspice 进行 仿真 ,再用Synopsys的awaves软件查看波形文件,或者用Sandwork公司 ...
个人分类: Hspice|4265 次阅读|4 个评论
分享 H$pice D-2010.03-SP1仿真Verilog-A文件的一个报错
wildgoat 2011-1-11 01:20
list文件中提示为: **error** call to epvaHDLcgen failed. google不到这样的错误提示,开始也怀疑是lic不全,后来觉得可能出在文件路径上。因为工作文件夹放在My Dropbox下,担心是文件名中的空格的原因。 再打开生成的*.valog文件,发现里面最后一句提示是*pvaE* 'd:/doc/my' file does not exist.。果然就是文件 ...
个人分类: Hspice|3926 次阅读|1 个评论
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