module debouncer
(
input key_in,
input clk_50m,
output reg key_out
);
reg [19:0] cnt;
reg sample_en;
always @ (posedge clk_50m)
begin
if (cnt >= 20'd999999)
cnt <= 20'd0;
else
cnt <= cnt + 20'd1;
end
always @ (posedge clk_50m)
begin
if (cnt == 20'd999999)
sample_en <= 1'b1;
else
sample_en <= 1'b0;
end
reg key_in_dly1;
reg key_in_dly2;
reg key_in_dly3;
always @ (posedge clk_50m)
begin
if (sample_en == 1'b1)
begin
key_in_dly1 <= key_in;
key_in_dly2 <= key_in_dly1;
key_in_dly3 <= key_in_dly2;
end
else ;
end
wire key_in_act;
wire key_in_deact;
assign key_in_act = key_in_dly1 || key_in_dly2 || key_in_dly3;
assign key_in_deact = key_in_dly1 && key_in_dly2 && key_in_dly3;
always @ (posedge clk_50m)
begin
if (key_in_act == 1'b0)
key_out <= 1'b0;
else if (key_in_deact == 1'b1)
key_out <= 1'b1;
else ;
end
endmodule