//march c- test flow
//↑W(0)↑R(0)W(1)↑R(1)W(0)
//↓R(0)W(1)↓R(1)W(0)↓R(0)
//↑: addr from 0 to max
//↓: addr from max to 0
//W(0): write "0"
//W(1): write "1"
//R(0): read expect "0"
//R(1): read expect "1"
`timescale 1ns/1ns
module march_c_test
(
input rst,
input clk,
input test_st
);
reg [9:0] addr;
reg en;
reg [2:0] cnt_march;
reg step_done;
//march c- cnt
//0: ↑W(0)
//1: ↑R(0)W(1)
//2: ↑R(1)W(0)
//3: ↓R(0)W(1)
//4: ↓R(1)W(0)
//5: ↓R(0)
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
cnt_march <= 3'd7;
else if (test_st == 1'b1)
cnt_march <= 3'd0;
else if (step_done == 1'b1)
cnt_march <= cnt_march + 3'd1;
else ;
end
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
en <= 1'b0;
else if (test_st == 1'b1)
en <= 1'b0;
else
en <= ~en;
end
always @ (*)
begin
case (cnt_march) //0: write 0, addr(0->1023)
3'd0: //1: read 0, write 1, addr(0->1023)
begin //2: read 1, write 0, addr(0->1023)
if (addr == 10'h3_ff)
step_done = 1'b1;
else
step_done = 1'b0;
end
3'd1, 3'd2:
begin
if (addr == 10'h3_ff && en == 1'b1)
step_done = 1'b1;
else
step_done = 1'b0;
end
//3: read 0, write 1, addr(1023->0)
3'd3: //4: read 1, write 0, addr(1023->0)
begin //5: read 0, addr(1023->0)
if (addr == 10'd0)
step_done = 1'b1;
else
step_done = 1'b0;
end
3'd4, 3'd5:
begin
if (addr == 10'd0 && en == 1'b1)
step_done = 1'b1;
else
step_done = 1'b0;
end
default: step_done = 1'b0;
endcase
end
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
addr <= 10'd0;
else if (test_st == 1'b1)
addr <= 10'd0;
else if (cnt_march == 3'd0)
addr <= addr + 10'd1;
else if (cnt_march == 3'd1)
begin
if (step_done == 1'b1)
addr <= 10'd0;
else if (en == 1'b1)
addr <= addr + 10'd1;
else ;
end
else if (cnt_march == 3'd2)
begin
if (step_done == 1'b1)
addr <= 10'd1023;
else if (en == 1'b1)
addr <= addr + 10'd1;
else ;
end
else if (cnt_march == 3'd3 || cnt_march == 3'd4)
begin
if (step_done == 1'b1)
addr <= 10'd1023;
else if (en == 1'b1)
addr <= addr - 10'd1;
else ;
end
else if (cnt_march == 3'd5)
addr <= addr - 10'd1;
else ;
end
reg wr_rd;
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
wr_rd <= 1'b0;
else
begin
case (cnt_march)
3'd0: wr_rd <= 1'b1; //write 0
3'd1, 3'd2, 3'd3, 3'd4:
begin
if (en == 1'b1)
wr_rd <= 1'b1;
else
wr_rd <= 1'b0;
end
3'd5: wr_rd <= 1'b0;
default: wr_rd <= 1'b0;
endcase
end
end
reg [17:0] data;
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
data <= 18'd0;
else if (test_st == 1'b1)
data <= 18'd0;
else if (cnt_march == 3'd1 || cnt_march == 3'd3)
data <= 18'h3ff;
else
data <= 18'd0;
end
reg [9:0] wr_addr;
reg [9:0] rd_addr;
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
wr_addr <= 10'd0;
rd_addr <= 10'd0;
end
else
begin
wr_addr <= addr;
rd_addr <= addr;
end
end
//wire [17:0] qout;
dpram
#(
.WIDTH ( 18 ),
.DEPTH ( 1024 ),
.OUT_REG("ENABLE" )
)u_dpram
(
.rst (rst ),
.clk_wr (clk ),
.clk_rd (clk ),
.wr_en (wr_rd ),
.rd_en (~wr_rd ),
.wr_addr (wr_addr),
.rd_addr (rd_addr),
.data (data ),
.q ( )
);
endmodule