module lvds_if
(
input rst,
input clk_122m88,
input wire lvds_clk_in,
input wire lvds_frame_in,
input wire [5 :0] lvds_data_in,
output wire [5 :0] lvds_data_out,
output wire lvds_clk_out,
output wire lvds_frame_out
);
wire sync_iq;
wire [11:0] dat_i1;
wire [11:0] dat_q1;
wire [11:0] dat_i2;
wire [11:0] dat_q2;
//----------------------------------------------------------------------------//
//
wire lvds_clk;
lvds_if_pll u_lvds_if_pll(
.refclk (lvds_clk_in), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (lvds_clk), // outclk0.clk
.locked () // locked.export
);
iq_ddr_rx u_iq_ddr_rx
(
.rst ( rst ),
.clk_122m88 ( clk_122m88 ),
.lvds_clk_in ( lvds_clk ),
.lvds_frame_in ( lvds_frame_in ),
.lvds_data_in ( lvds_data_in ),
.sync_iq ( sync_iq ),
.dat_i1 ( dat_i1 ),
.dat_q1 ( dat_q1 ),
.dat_i2 ( dat_i2 ),
.dat_q2 ( dat_q2 )
);
//----------------------------------------------------------------------------//
iq_ddr_tx u_iq_ddr_tx
(
.rst ( rst ),
.clk_122m88 ( clk_122m88 ),
.sync_iq ( sync_iq ),
.dat_i1 ( dat_i1 ),
.dat_q1 ( dat_q1 ),
.dat_i2 ( dat_i2 ),
.dat_q2 ( dat_q2 ),
.lvds_data_out (lvds_data_out ),
.lvds_clk_out (lvds_clk_out ),
.lvds_frame_out (lvds_frame_out)
);
//----------------------------------------------------------------------------//
endmodule
module iq_ddr_rx
(
input rst,
input clk_122m88,
input wire lvds_clk_in,
input wire lvds_frame_in,
input wire [5 :0] lvds_data_in,
output reg sync_iq,
output reg [11:0] dat_i1,
output reg [11:0] dat_q1,
output reg [11:0] dat_i2,
output reg [11:0] dat_q2
);
wire frame_h;
wire [5:0] din_h;
wire [5:0] din_l;
reg [5:0] din_h_dly;
reg [5:0] din_l_dly;
reg frame_dly;
wire [5:0] qout_i;
wire [5:0] qout_q;
wire qout_f;
reg [5:0] dat_i;
reg [5:0] dat_q;
reg [5:0] dat_i_dly;
reg [5:0] dat_q_dly;
reg frame_l;
reg frame_l_dly;
reg frame_r;
reg frame_f;
reg [11:0] data_i1;
reg [11:0] data_q1;
reg [11:0] data_i2;
reg [11:0] data_q2;
alt_iddr
#(
.DATA_WIDTH(1)
)u0_alt_iddr
(
.aclr (rst),
.datain (lvds_frame_in),
.inclock (lvds_clk_in),
.dataout_h (frame_h),
.dataout_l ()
);
alt_iddr
#(
.DATA_WIDTH(6)
)u1_alt_iddr
(
.aclr (rst),
.datain (lvds_data_in),
.inclock (lvds_clk_in),
.dataout_h (din_h),
.dataout_l (din_l)
);
always @ (posedge lvds_clk_in or posedge rst)
begin
if (rst == 1'b1)
begin
din_h_dly <= 6'd0;
din_l_dly <= 6'd0;
frame_dly <= 1'b0;
end
else
begin
din_h_dly <= din_h;
din_l_dly <= din_l;
frame_dly <= frame_h;
end
end
alt_fifo u_alt_fifo
(
.data ({1'b0,frame_dly,din_l_dly,din_h_dly}),
.rdclk (clk_122m88),
.rdreq (1'b1),
.wrclk (lvds_clk_in),
.wrreq (1'b1),
.q ({qout_f,qout_i,qout_q}),
.rdempty (),
.wrfull ()
);
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
begin
dat_i <= 6'd0;
dat_q <= 6'd0;
dat_i_dly <= 6'd0;
dat_q_dly <= 6'd0;
frame_l <= 1'd0;
end
else
begin
dat_i <= qout_i;
dat_q <= qout_q;
dat_i_dly <= dat_i;
dat_q_dly <= dat_q;
frame_l <= qout_f;
end
end
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
frame_l_dly <= 1'b0;
else
frame_l_dly <= frame_l;
end
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
begin
frame_r <= 1'b0;
frame_f <= 1'b0;
end
else
begin
frame_r <= frame_l && (~frame_l_dly);
frame_f <= (~frame_l) && frame_l_dly;
end
end
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
begin
data_i1 <= 12'd0;
data_q1 <= 12'd0;
end
else if (frame_r == 1'b1)
begin
data_i1 <= {dat_i_dly,dat_i};
data_q1 <= {dat_q_dly,dat_q};
end
else ;
end
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
begin
data_i2 <= 12'd0;
data_q2 <= 12'd0;
end
else if (frame_f == 1'b1)
begin
data_i2 <= {dat_i_dly,dat_i};
data_q2 <= {dat_q_dly,dat_q};
end
else ;
end
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
begin
dat_i1 <= 12'd0;
dat_q1 <= 12'd0;
dat_i2 <= 12'd0;
dat_q2 <= 12'd0;
end
else if (frame_r == 1'b1)
begin
dat_i1 <= data_i1;
dat_q1 <= data_q1;
dat_i2 <= data_i2;
dat_q2 <= data_q2;
end
else ;
end
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
sync_iq <= 1'b0;
else
sync_iq <= frame_r;
end
endmodule
module iq_ddr_tx
(
input rst,
input clk_122m88,
input sync_iq,
input [11:0] dat_i1,
input [11:0] dat_q1,
input [11:0] dat_i2,
input [11:0] dat_q2,
output wire lvds_clk_out,
output wire lvds_frame_out,
output wire [5 :0] lvds_data_out
);
reg [5:0] data_i;
reg [5:0] data_q;
reg [1:0] cnt_3;
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
cnt_3 <= 2'd0;
else if (sync_iq == 1'b1)
cnt_3 <= 2'd0;
else
cnt_3 <= cnt_3 + 2'd1;
end
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
begin
data_i <= 6'd0;
data_q <= 6'd0;
end
else
begin
case(cnt_3)
2'd3: begin
data_i <= dat_i1[11:6];
data_q <= dat_q1[11:6];
end
2'd0: begin
data_i <= dat_i1[5:0];
data_q <= dat_q1[5:0];
end
2'd1: begin
data_i <= dat_i2[11:6];
data_q <= dat_q2[11:6];
end
2'd2: begin
data_i <= dat_i2[5:0];
data_q <= dat_q2[5:0];
end
endcase
end
end
reg frame;
always @ (posedge clk_122m88 or posedge rst)
begin
if (rst == 1'b1)
frame. <= 1'b0;
else if ((cnt_3 == 2'd3) || (cnt_3 == 2'd0))
frame. <= 1'b1;
else
frame. <= 1'b0;
end
alt_oddr
#(
.DATA_WIDTH(1)
)u0_alt_oddr
(
.aclr (rst),
.datain_h (1'b1),
.datain_l (1'b0),
.outclock (clk_122m88),
.dataout (lvds_clk_out)
);
alt_oddr
#(
.DATA_WIDTH(1)
)u1_alt_oddr
(
.aclr (rst),
.datain_h (frame),
.datain_l (frame),
.outclock (clk_122m88),
.dataout (lvds_frame_out)
);
alt_oddr
#(
.DATA_WIDTH(6)
)u2_alt_oddr
(
.aclr (rst),
.datain_h (data_i),
.datain_l (data_q),
.outclock (clk_122m88),
.dataout (lvds_data_out)
);
endmodule