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usb的verilog代码
热度 1| |
module USB ( rst ,
clk,
fifo_wr ,
fifo_rd ,
fifo_data,
fifo_pf,
fifo_full,
fifo_empty,
);
input rst ;
input clk ;
input fifo_pf,fifo_full,fifo_empty;
output[7:0] fifo_data ;
output fifo_wr ;
output fifo_rd ;
//ports
wire rst ;
wire clk ;
reg [7:0] fifo_data ;
reg fifo_wr ;
reg fifo_rd ;
//internal signals
reg clkin;
reg [2:0] STATE,NEXT;
//parameters
parameter IDLE = 3'D0,
WRITE_1 = 3'D1,
WRITE_2 = 3'D2;
//Div clk by 2
always @ (posedge clk or negedge rst)
begin
if(!rst)
clkin <= 'b1;
else
clkin <= ~clkin;
end
//state machine
always @ (STATE or rst)
begin
case(STATE)
IDLE : NEXT = WRITE_1;
WRITE_1 : if(!fifo_full)
NEXT = WRITE_1;
else
NEXT = WRITE_2;
WRITE_2 : NEXT = WRITE_1;
default : NEXT = IDLE ;
endcase
end
//registe the state
always @ (posedge clkin or negedge rst)
if(!rst)
STATE <= IDLE;
else
STATE <= NEXT;
always @ (posedge clkin or negedge rst)
if(!rst)
begin
fifo_data <=8'hff;
fifo_wr <=1'b1;
fifo_rd <=1'b1;
end
else
case(STATE)
IDLE : begin
fifo_rd <= 1;
fifo_wr <= 1;
end
WRITE_1 : begin
if(fifo_full)
fifo_data <= fifo_data + 1;
fifo_wr <= 1'b0;
fifo_rd <= 1'b1;
end
WRITE_2 : begin
fifo_wr <= 1'b1;
fifo_rd <= 1'b1;
end
endcase
endmodule
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