1. What is a logic-1 or a logic-0? (1) In a CMOS cell, two values VIHmin and VILmax define the limits. That is, any voltage value above VIHmin is considered as a logic-1 and any voltage value below VILmax is considered as a logic-0. 2. What's the inputs and output capacitance? ...
1.What is Static Timing Analysis? 1) Static Timing Analysis (also referred as STA) is one of the many techniques available to verify the timing of a digital design. 2) The STA is ...
Reference: PrimeTime_AOCV_APPNote_6.0.pdf 1. What's the difference between OCV and AOCV? (1) OCV(on-chip variations):using a global derating value to add design margin (2) AOCV:AOCV models the random and systematic variations across an IC that affect timing ...
Link: https://www.eetimes.com/document.asp?doc_id=1278980 A latch is a level-sensitive storage cell that is transparent to signals passing from the D input to output Q when enabled, and that holds the values of D on Q as of the time enable goes False. The enabled state is also called transpare ...
1. Parse report_timing command (1) What's "time borrowed from endpoint" and "time given to startpoint"? Link:http://www.xilinx.com/support/answers/56877.html Time borrowed from endpoint: In a path where the endpoint is a latch device, the borrowing time ...