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分享 Chapter3(Standard Cell Library ) of Static Timing Analysis for Nanometer Designs
ghong6003 2018-1-30 14:51
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个人分类: STA|1053 次阅读|0 个评论
分享 Chapter2(STA Concepts ) of Static Timing Analysis for Nanometer Designs
ghong6003 2018-1-30 10:38
1. What is a logic-1 or a logic-0? (1) In a CMOS cell, two values VIHmin and VILmax define the limits. That is, any voltage value above VIHmin is considered as a logic-1 and any voltage value below VILmax is considered as a logic-0. 2. What's the inputs and output capacitance? ...
个人分类: STA|2844 次阅读|0 个评论
分享 Glossary
ghong6003 2018-1-26 16:35
ASIC : Application Specific Integrated Circuit AOCV : Advanced on-chip Variation(back_end STA) CPLD : Complex Programmable Logic Device CRPR: clock reconveregence pessimism removal(Synopysis, same with CPPR) CPPR: clock path pessimism removal(Cadence, ...
626 次阅读|0 个评论
分享 Chapter1(Introduction ) of Static Timing Analysis for Nanometer Designs
ghong6003 2018-1-25 22:36
1.What is Static Timing Analysis? 1) Static Timing Analysis (also referred as STA) is one of the many techniques available to verify the timing of a digital design. 2) The STA is ...
个人分类: STA|7448 次阅读|0 个评论
分享 AOCV:Advanced On-Chip Variation
ghong6003 2018-1-25 16:33
Reference: PrimeTime_AOCV_APPNote_6.0.pdf 1. What's the difference between OCV and AOCV? (1) OCV(on-chip variations):using a global derating value to add design margin (2) AOCV:AOCV models the random and systematic variations across an IC that affect timing ...
个人分类: STA|5065 次阅读|0 个评论 热度 2
分享 Latch vs flipflop
ghong6003 2018-1-19 16:31
Link: https://www.eetimes.com/document.asp?doc_id=1278980 A latch is a level-sensitive storage cell that is transparent to signals passing from the D input to output Q when enabled, and that holds the values of D on Q as of the time enable goes False. The enabled state is also called transpare ...
个人分类: STA|1124 次阅读|0 个评论
分享 STA Constraints
ghong6003 2018-1-19 16:17
######################################### # Clock define command and parameters ######################################## (1) create_clock (2) create_generated_clock NAME create_generated_clock &nb ...
个人分类: STA|2357 次阅读|1 个评论 热度 1
分享 Questions about STA and Report
ghong6003 2018-1-19 12:56
1. Parse report_timing command (1) What's "time borrowed from endpoint" and "time given to startpoint"? Link:http://www.xilinx.com/support/answers/56877.html Time borrowed from endpoint: In a path where the endpoint is a latch device, the borrowing time ...
个人分类: STA|1710 次阅读|0 个评论
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