1. regression list process 1.1 each line shall chop the "\t" and space in the beginning and end. 1.2 leave only one space between two words. 2. perl5: 2.1 perl5 support OOP with "package" 2.2 or比||优先级低 & ...
1. 3-step flow -- for mixed vhdl and verilog language vhdlan -f vhdl_file_list vlogan uvm // need to compile uvm independently vlogan -f rtl_file_list simv
象下面用继承+factory实现callback的方法,导致unmanageable explosion of driver class class driver extends uvm_driver #(packet); `uvm_component_utils(driver) function new(string name, uvm_component parent); super.new(name, parent); & ...
dve has interactive mode and post-process mode: interactive mode: start dve and control simulator (vcs) to run 1. simv -gui 2. simv -ucli 3. vcs -gui -R 4. dve -toolexe name -toolargs simulator args post-process mode: run simulation and use dve to check waveform. or coverage ...