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shift_dly
| |
module shift_dly
#(
parameter DLY_DISTANCE = 3,
parameter DATA_WIDTH = 8
)
(
input rst,
input clk,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout
);
generate
if (DLY_DISTANCE == 1)
begin: DLY1
reg [DATA_WIDTH-1:0] din_dly;
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
din_dly <= {DATA_WIDTH{1'b0}};
else
din_dly <= din;
end
assign dout = din_dly;
end
else
begin: DLY_MORE
reg [DLY_DISTANCE*DATA_WIDTH-1:0] din_dly;
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
din_dly <= {DLY_DISTANCE*DATA_WIDTH{1'b0}};
else
din_dly[DLY_DISTANCE*DATA_WIDTH-1:0] <= {din_dly[(DLY_DISTANCE-1)*DATA_WIDTH-1:0],din};
end
assign dout = din_dly[DLY_DISTANCE*DATA_WIDTH-1:(DLY_DISTANCE-1)*DATA_WIDTH];
end
endgenerate
endmodule
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