大神共65张投影片，解说得很好
https://www.slideshare.net/shavakmm/lowpowerseminar810

一个测试范例的综合品质成果(QoR)。


附简单中文翻译的解说：
1) What are High-Vt and Low-Vt cells?
Ans: 
Hvt  cells are MOS devices with less leakage due to high Vt but they have  higher delay than low VT, where as the low Vt cells are devices, which  have less delay, but leakage is high. 
HVT 的漏电流比较小但有比较长的延迟, LVT的延迟比较短但是漏电流比较大。
The  threshold (t) voltage dictates the transistor switching speed, it  matters how much minimum threshold voltage applied can make the  transistor switching to active state, which results to how fast we can  switch the transistor.
 Vt电压跟transistor切换速度有关. 电压越低切换越快。 Disadvantage  is it needs to maintain the transistor in a minimum sub threshold  voltage level to make it switch fast so it leads to leakage of current  in turn loss of power.
缺点是会导致漏电流变大。
2) Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits
Ans:
1) In digital design, decide the height of standard cells you want to layout. It depends upon how big your transistors will be.
 layout的结果中你要的标准cell height根据你的transistor要多大  Have reasonable width for VDD and GND metal paths.
VDD, GND的metal路径宽度要合理
Maintaining  uniform Height for all the cell is very important since this will help  you use place route tool easily and also incase you want to do manual  connection of all the blocks it saves on lot of area.
cell中的高度要保持一样是非常重要, 因为使用route tool时变的简单 或者是手动控制block时的时候也可节省面积
2)  Use one metal in one direction only; this does not apply for metal 1.  Say you are using metal 2 to do horizontal connections, and then use  metal 3 for vertical connections, metal4 for horizontal, metal 5  vertical etc...
一个方向只用一种metal
3) Place as much substrate contact as possible in the empty spaces of the layout.
在layout空白处放substrate contact越多越好
4) Do not use poly over long distances as it has huge resistances unless you have no other choice.
尽量不要把poly弄得太长, 它会增加电阻
5) Use fingered transistors as and when you feel necessary.
6) Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.