HD (High Density) --- 7-track
HP (High Performance) --- 10-track, however, for N90 libraries, HD = 9-track
UHP (Ultra High Performance) --- 11-track

什么是7/8/9/10/11/12-track?



OR

T*** 40nm
CMOS Low Power (AL_RDL SALICIDE CU_ELK 1.1/2.5V), core cell library,
standard Vt, 9-track, tapless cell layout structure, support multi-Vdd,
raw gate density = 2000 Kgates/mm^2, direct shrink from 45nm with shrink factor = 0.9

A4: one
track is approximately the minimum spacing between metal1 and metal1
via in a technology node . Track is generally used as a unit to define
the height of the std cell. a 12 track cell will be taller than a 9
track cell. a 12 track std cell will be taller , that means more metal1
routing space is available within the cell, hence cells will be faster.
where as in a 9 track cell, the cell will be compact, but speed is less
compared to 12 track.
9-track -> less area, less speed compared to 12 track.
12-tarck -> more area, more speed compared to 9 track.

Suppose
you have a NAND gate. Now with same W/Ls of transitor if you make
layout in 9 tracks and 12 tracks, then 12 track NAND gate layout would
be somewhat in thinner but taller by 33.33%. Since it is taller that
means there is more space horizontally available for routing over this
12 track cell compared to 9 track cell.
Bigger cells has better
driving capability , than their equivalent normal cells . i.e they will
be faster than their normal counter parts.