ESD protection for RF Applications

1. Introduction

Electrostatic Discharge (ESD) events occur to balance the charge between two objects. The movement of these charges occurs very rapidly., leading to high currents. When the current passes through an object, the impedance of that object establishes a voltage across it. The voltage establishes an electric field in the surrounding objects based on the geometry and dielectric material present in the structure. Both high current densities and high electric fields cause damage on semiconductor devices.

Fig.1 shows a pareto chart of the failure causes for all the field returns analyzed; ESD represents a sizable percentage. Wagner et al. reported ESD as being the cause of greater than 25% of the failures encountered. These data show a great opportunity for improvement with respect to ESD/EOS related failures.

Electrostatic Discharge (ESD) phenomena in integrated circuits (IC) have grown in importance as technologies shrink to below 0.5 um dimensions. The ESD protection method for RF integrated circuits becomes more important as operation frequencies increase. The capacitance associated with the ESD protection is therefore progressively becoming a bottleneck.

Fig. 2 explains that the introduction of each new generation of silicon technology results in new challenges in terms of ESD capability and protection circuit design. Figure 1 shows how ESD performance for specific protection circuits has changed over period time. Initially the ESD performance improves as the circuit designs mature and problems are solved or debugged. After a certain time the technology changes caused the circuit to no longer function to its original capability and new protection techniques are needed to restore good ESD performance. As a result, the ESD issue is expected to remain important for the foreseeable future of IC technology. The speed with which new technologies are introduced has reduced the available time for protection circuit development. In fact it is becoming more and more important to design circuits which can be transferred into the newer technologies with minimum changes. Hence, it is necessary to understand the main issues involved in ESD protection circuit design and the physical mechanisms taking place in order to ensure that the design can be scaled or transferred with minimum impact on the ESD performance.

2. ESD test method

 To measure the ESD survival level of the RFIC and ESD protection devices, we need the international ESD standard model. Generally, HBM(Human Body Model), MM(Machine Model) and CDM(Charged Device Model) are used to measure the ESD survival level of the RFIC and ESD protection devices. The HBM ESD event describes a discharge procedure where a charged human body contacts a device directly and electrostatic charges transfer from the human body into the device. The MM ESD events occur when metallic machinery contacts IC components in an IC manufacturing environment. Typical such actions include in-line inspection and automatic test equipment. CDM depicts an ESD event, different from that of HBM type, where a charged IC part discharges when a pin contacts a grounded object or conductive surface. The CDM pre-charging occur often manufacturing and field application environments.

 The HBM, shown Fig. 3, is the ESD testing standard, and is defined in the MIL-STD-883C method 3015.7. The discharge wave form. of an HBM tester through a 0 Ω load is shown in Fig. 3 (b). The rise time is approximately 10 nsec, and the decay time is around 150nsec. The waveform. is obtained by the discharge of a 100pF capacitor with an initial voltage of 2kV through a 1.5 kΩ resistor. The HBM can be modeled using the LCR circuit shown in Fig. 3.

The MM is the standard ESD test method in Japan, and this has driven its usage amongst US and European IC manufacturers. The MM discharge circuit can be defined by the LCR network in Fig. 4. The MM is similar to the HBM, with the substitution of a 750 nH inductor for 1.5 kΩ resistor, increasing the capacitance to 200 pF. This model is intended to represent the type of damage caused by equipment used in manufacturing. It represents a worst cause HBM event and produces damage similar to the HBM but at much lower threshold levels. The inductance value in the model is the most critical parameter because it controls the rise time of the current during the discharge.

 The CDM is the newest model and also the most difficult to reproduce. It is very sensitive to parasitics in the test hardware. This model is intended to simulate the event that occurs from a charged packaged part’s subsequently discharging into low impedance ground. This ground can be a hard grounded surface or a large charge sink like a metal work table or tool. This could occur during testing where a part is triboelectrically charged in handler. When the part comes into contact with the tester’s pins, it discharges. The discharge impedance in real life is close to zero, but it is finite and small in and ESD tester. This is where the variability between testers comes into ply. The peak currents are much higher than in the HBM and the rise times as well as the duration is much shorter. The rise time is limited by the inductance and resistance in the current path. For many packages, this is the bond wire impedance of ~ 0.5 nH.

       3. ESD protection for RF applications

 The parasitic I/O capacitance which is often dominated by ESD in a stage-of-art CMOS technology is typically in the range 2 to 8 pF. At radio frequency, the reactance associated with this large capacitance becomes comparable to the 50-ohm characteristic impedance of the package and board interfaces. This causes significant reflections and severely limits the chip-to-chip signal bandwidth. There is therefore only limited or no ESD protection in multi-GHz design. However, yield loss due to ESD failures is expected to become increasingly important as high-volume designs enter the GHz regime.

 The conventional ESD protection method is shown in fig 6. The primary element will shunt most or all of the current during an ESD event, while the secondary element serves to limit the voltage or current at the circuit being protected until the primary device is fully operational. The two elements are isolated by a resistive element. This isolation resistor will limit the current toward the secondary stage and core circuits.

This conventional ESD protection method is often applied for digital circuits and analog circuits. But, for RF applications, the isolation resistor is too large to be located in the RF signal line. The power of signal can be dissipated severely in the large isolation resistor. So this topology must be modified to be applied for RFIC, like Fig 7. But the absent of isolation resistor degrade the ESD survival level of whole RFIC. Because there is no isolation resistor in Fig. 7, the ESD current can reach the core circuits more easily. So, to get high ESD survival level of whole chip, the ESD protection device of Fig. 7 must shunt the ESD current very effectively. Then, the size of ESD protection device should be very large. But this very large ESD protection device will cause the very large parasitic shunt capacitance during the normal operation of core circuits. And these large parasitic capacitance induced by the ESD protection device will degrade the RF performance of core circuits. So ‘high ESD survival level’ and ‘good RF characteristics’ are trade-off relations.

4. ESD Protection device

 In this chapter, the various ESD protection devices will be introduced. The ggMOS(grounded MOSFET), gcMOS(gate-coupled MOSFET), BJT and diode etc. can be used as ESD protection devices. At first the ESD failure mechanism will be discussed briefly. Next the operation of each ESD protection devices will be discussed.

The two main ESD failure mechanisms are associated with thermal damages and dielectric failures. The root cause to thermal damage is the very high transient current generated by an ESD pulse. Since semiconductors, e.g., silicon, are normally poor thermal conductors, the heat generated by large ESD currents cause temperature increase in both silicon and metal interconnect materials. The situation is even worse because heat generators are usually located near the surface covered by very poor thermal conductive silicon dioxide films. Because of the transient nature of ESD events, the heat generated has little chance to be dissipated. Consequently, ESD damages occur as highly localized thermal defects in both silicon and metals. On the other hand, dielectric failures are caused by high electric field induced dielectric breakdown, often occurring in MOSFET gate oxide layers. For example, given typical SiO₂ dielectric strength of 8 ~10 MV/cm gate oxide of 35 A in a 0.18 um CMOS technology could be damaged by a bias of less than 4V.

 Having known the root causes to ESD damages, one ought to deal with both large currents and high voltage in ESD protection design. Therefore the principle of on-chip ESD protection solutions is two-fold: to safely discharge ESD currents via a low-impedance shunting path and to clamp a bond pad voltage to a sufficiently low level. There are two general means to realize the above ESD protection concepts, as illustrated Fig. 9. The first option is to use a protection device with a simple turn-on I-V characteristic as shown in Fig. 9 (a), where the protection unit is turned on at threshold point (V_t1, I_t1) with t1 being the triggering time and forms a voltage V_t1 should be sufficiently low for voltage clamping, however, shall be greater than operation voltage of the IC chip, i.e., V_DD, to avoid accidental turn-on under normal operation. The current handling capability, reflecting the ESDV level, is only limited by heat generation due to series resistance in the shunting channel. This type of ESD protection devices can be readily included into circuit simulation. The second solution is based upon a snapback I-V characteristic as depicted in Fig. 9 (b), where a protection element is turned on at a triggering point (V_t1, I_t1, t1), then driven into a snapback region with low holding (V_h, I_h) to create a low-impedance discharge path. The trigger voltage V_t1 is designed according to the IC chip. The holding voltage V_h shall ensure proper voltage clamping and the holding current I_h is selected with latch-up in consideration. A deep snapback I-V is therefore preferable for better ESD protection. The ESD protection performance level, i.e, ESDV value, is typically represented by the second breakdown (or, thermal breakdown) current I_t2. While early-day ESD protection usually resorts to the simple turn-on type protection devices, such as forward junction diodes; a snapback type protection is more efficient and gaining popularity nowadays. However, a main disadvantage of the snapback type design is that it cannot be included in circuit simulation. It is worth to point it out that critical aspect in rational ESD protection design shall be to properly and accurately select the triggering point (V_t1, I_t1, t1), holding point (V_h , I_h) and second breakdown threshold (V_t2, I_t2), which are key parameters in ESD protection circuit design. Most ESD protection solutions are developed based upon the above two principles. Typical ESD protection devices, being the building bricks for all ESD protection networks, are discussed in the following sections in details, with more sophisticated ESD protection circuits to be discussed in next section

4.1 Grounded gate MOS (ggMOS)

 MOS field effect transistor (MOSFET) is currently the most widely used ESD protection structures because of its active discharge mechanism and compatibility to CMOS technologies. However, design of MOS ESD protection for high ESD protection performance ( > 2kV ) is not an easy task.

One of the simplest MOS ESD protection device is the so-called grounded-gate NMOS ( ggNMOS ) structure, where the drain (D) goes to an I/O pad and the gate (G), source (S) and body (B) are shortened together to ground. The Fig. 10 illustrates its typical cross-section and equivalent circuit. The principle of a ggNMOS in ESD protection operation follows. As a positive ESD transient appears at an I/O pad, i.e., D, with respect to ground, the DB junction is reverse-biased all the way to its breakdown. Avalanche multiplication takes place and generates electron-hole pairs. The Hole current flows into the ground via the B-region and build up a potential, V_R, across the lateral parasitic resistance R. Since the B and S regions are shortened together, V_R actually appears across the BS PN junction positively. As VR increases, the BS junction turns on, eventually triggers the parasitic lateral NPN transistor Q (DBS).As result, the ggNMOS is turned on at a triggering point, V_t1, under ESD pulse; moves into a snapback region to form. a low-impedance discharge channel with low holding voltage, V_h; hence, discharges ESD transients safely. Clearly, the efficiency of this ggNMOS as an ESD protection structure is determined by the parasitic NPN BJT behavior. Should a negative ESD pulse comes to the I/O pad, a forward-biased parasitic diode, BD, will take the role to shunt the transient. One of the main reasons for grounding the gate is to ensure “zero” leakage of the ESD protection structure under normal operations.

 This ggNOMS ESD protection structure has several advantages. Firstly, it provides an active discharging path, although in one direction only. Secondly, it is a natural option in CMOS technologies. There are disadvantages as well. For example, it cannot be included into circuit simulation due to its snapback I-V behavior. Its application is also limited when being used as a complete ESD protection device because of the forward parasitic diode turn-on, which is too low for many high voltage applications

4.2 Gate-coupled MOS (gcMOS)

 Looking at any ESD protection layout using MOS protection structures, one can find that a big chuck of finger structures is usually used. The reason for that is to ensure high ESD protection by maintaining uniform. current distribution, fairly similar to designing a large output buffer transistor. Because of its relatively lower ESD protection rating of a MOS protection structure, a fairly large device may be needed to realize high ESD protection level. For example, a 400um wide NMOS structure may be needed in order to achieve 8kV ESD protection in HBM mode in a robust 20V/um-width NMOS ESD technology. Unfortunately, it is not feasible to retain a wonderful relationship for the ESD protection level and the device size in practical design because of operation defects, such as current crowding, etc. It is normally suggested that the channel width of a single MOS transistor, or preferably called finger length by an ESD designer, should be between 40um to 100um. Using a multiple-finger, or ladder, structure is a straightforward solution to this problem in design practices. However, it is still difficult to achieve the NMOS protection structure size to the ESD protection level scalability as expected, if cares are not exercised in both design and layout. This skewed finger-number-to-ESD-protection relationship is one of the most trouble-some design problem in designing the multiple-finger type MOSFET ESD protection structures.

 The reason is that Murphy’s Law always prefers to turn on one MOSFET finger ahead of any other ones. If the I-V characteristic of a ggNMOS ESD protection structure follows the solid-line as in Fig.11 (a), where trigger voltage V_t1 is greater that thermal breakdown voltage V_t2, i.e. V_t1>V_t2, it is easy to image the first turned on MOSFET finger starts to discharge the ESD transients and would reach to its damage threshold before any other fingers come into play. In such a case, simply increase of the number of MOSFET fingers would not offer a designer anything useful other than producing extra parasitic effects and consuming more silicon, which is particularly true in any silicided technology. To resolve this problem, a commonly accepted design principle is that one should make trigger voltage Vt1 less than thermal breakdown voltage V_t2, i.e., V_t1<V_t2, as shown by the I-V curve in dashed-line in Fig. 11 (a). This way, before the on-finger has a chance reach to its thermal failure threshold, all other fingers can be turned on and join the game to discharge the ESD transients, at least in theory. Alternatively, one may insert ballasting resistor into each NMOS finger to ensure uniform. turn on, as illustrated in Fig. 11 (b) as well. Since one usually has only limited cards to play in reducing V_t1 in a specific technology, circuit techniques, such as the gate coupling technique is often used in designing multiple-finger MOSFET ESD protection structures.

Having known that an ideal design of V_t1 < V_t2 is desired to make a multiple-finger NMOS ESD protection structure a useful solution. A gate-coupling technique is one of the most commonly used schemes in realizing the V_t1 < V_t2 design. Fig. 13 shows some of the gate-coupled NMOS ESD protection examples. In Fig. 13 (a), a RC coupling branch is connected to the gate of a NMOS protection device to bias up the gate. Its operation mechanism follows. As a positive ESD pulse appears at the input pad with respect to ground, the transient pulse is coupled onto the NMOS gate and readily raises gate voltage, Vg, to some level, which results in a reduced trigger voltage Vg. Assuming this theory holds, it would be possible to realize the desired V_t1 < V_t2 condition by proper designing the gcNMOS network. Consequently, all fingers can be turned on before any one of them might have a chance to reach to its thermal damage point, V_t2.

4.3 SCR

One of the main hurdles impeding the use of SCR as ESD protection structure is that its trigger voltage is usually too high in normal CMOS processes for non-high-voltage applications. However, SCR emerges back as an attractive ESD protection option because of its high area efficiency that is highly desirable to parasitic-sensitive RF and high-pin-count ICs. Certainly, the high trigger voltage problem is getting worse in low-voltage very-deep-sub-micron(VDSM) applications. This is where ESD protection circuits, instead of stand-alone devices, come into play. Many SCR-based ESD protection circuit schemes, using trigger-assisting sub-networks, were devised to achieve low-V_t1 SCR ESD protection.

4.4 diode

The MOSFET is most widely used ESD protection device as the very widely usage of improved CMOS processes. But using the MOSFET as ESD protection devices for RF applications must be considered very carefully. The parasitic effect of ESD devices would degrade the power gain S21 and increase the noise figure in RF circuits. So, the input port ESD devices need special design considerations. There are some requests for ESD protection devices in RF integrated circuits; low parasitic capacitance, constant input capacitance, insensitive to substrate coupling noise and good ESD performance. The traditional input port ESD device is the gate-grounded NMOS. The ggMOS is often designed with a large device dimension and wider drain-contact-to-poly-gated layout spacing to sustain an acceptable ESD level. To further improve ESD level of the MOSFET with a large device dimension, the gate coupled circuit technique or the substrate-triggering circuit technique had been designed to uniformly trigger on the multiple fingers of the ESD protection MOSFET. Besides, the additional silicide-bolcked mask had been included into deep submicron CMOSFET process to increase ESD robustness of the ESD clamp device. The schematic cross-sectional view of a ggMOS with the silicide-blocked mask had been included into the deep submicron CMOS process to increase ESD robustness of the ESD clamp device. But the ggMOS with a larger devices dimension and a wider drain diffusion junction contributes a larger parasitic drain capacitance to the input pad the overlapped gate-to-drain capacitance also contributes to the input pad. So, such ggMOS is not suitable for RF ESD applications. Recently, some works shows that the diode is more suitable as ESD protection deivce for RF applications. Among these works this STI diodes and ploy-gated diode will be introduced in this section.

Diodes had been commonly used as ESD protection devices. The working regions can be distinguished as two parts: the forward bias region and the reverse bias region. Under the forward bias re