日志
乘法器verilog
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module mux(altremote_reconfig, altremote_busy, in_altremote, in_updatelogic, out_altasmi);
input altremote_reconfig;
input altremote_busy;
input in_altremote; //This need to be assigned according to the respective outputs from altremote_update that need to be multiplexed
input in_updatelogic; //This need to be assigned according to the respective outputs from update logic that need to be multiplexed
output out_altasmi;
wire out_altasmi;
reg remote_access;
assign out_altasmi = remote_access? in_altremote: in_updatelogic;
always @(posedge altremote_reconfig)
begin
remote_access <= 1'b1;
end
always @(negedge altremote_busy)
begin
remote_access <= 1'b0;
end
endmodule
module mux_tb ();
reg altremote_reconfig;
reg altremote_busy;
reg in_altremote; //This need to be assigned according to the respective outputs from altremote_update that need to be multiplexed
reg in_updatelogic; //This need to be assigned according to the respective outputs from update logic that need to be multiplexed
wire out_altasmi;
initial
begin
altremote_reconfig = 1'b0;
#150 altremote_reconfig = 1'b1;
#180 altremote_reconfig = 1'b0;
end
initial
begin
altremote_busy = 1'b0;
#20 altremote_busy = 1'b1;
#100 altremote_busy = 1'b0;
#200 altremote_busy = 1'b1;
#300 altremote_busy = 1'b0;
end
mux muxinst(altremote_reconfig, altremote_busy, in_altremote, in_updatelogic, out_altasmi);
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