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DGO&TGO

已有 3918 次阅读| 2019-12-23 11:03 |个人分类:technology|系统分类:芯片设计

DGO:Dual Gate Oxide process

TGO:Triple Gate Oxide process

As complementary metal oxide semiconductor (CMOS) logic scales down, it needs ultrathin gate oxides and a reduced operating voltage for high performance. At the same time, however, an increasing number of applications require dual voltage or dual gate oxide (DGO) on a chip to interface to a higher external voltage. Moreover, to facilitate merged logic and memory circuits, DGO for memory and logic is also required. In a conventional DGO process using wet etching, a thick oxide layer is formed by reoxidizing the residual oxide after partially etching the pregrown oxide, while a thin oxide layer is grown on a clean silicon surface after thoroughly etching the pregrown oxide. Thus, the thick oxide layer in the DGO process has a tendency to poor reliability compared with a thin oxide layer and single-step-grown oxide with the same thickness.

随着互补金属氧化物半导体(CMOS)逻辑规模的缩小，它需要超薄栅氧化物和降低的工作电压来实现高性能。然而，与此同时，越来越多的应用需要双电压或双栅氧化物(DGO)芯片接口到更高的外部电压。此外，为了方便合并的逻辑和存储电路，DGO的内存和逻辑也是必需的。在传统的DGO湿法蚀刻工艺中，先对预生长的氧化物进行局部蚀刻，然后对剩余的氧化物进行再氧化，形成较厚的氧化层，而在对预生长的氧化物进行彻底蚀刻后，在干净的硅表面形成较薄的氧化层。因此，与同厚度的薄氧化层和单级氧化层相比，DGO工艺中的厚氧化层可靠性较差。

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Why Triple Oxide?

As process geometries have shrunk, and transistors became smaller and thus cheaper, the gate oxide (the layer of silicon-dioxide that separated the gate from source and drAIn) had to be made thinner to achieve high switching speed. But thin oxide (down to 16 Å = 1.6 nm) cannot tolerate a voltage that is higher than about 1.5 V. (Excessive voltage leads to degradation over time, especially at elevated temperatures, and we expect our circuits to stay within specification for at least 20 years).

That is why Vccint has been reduced to 1.2 V for Virtex-4 and to 1.0 for Virtex-5 devices.

Thin oxide is necessary for high performance, and important for low dynamic power consumption, but it also causes the leakage current to increase dramatically. There are two components to the leakage current: gate leakage current which just passes through the very thin gate oxide, and source-drain leakage which is caused by transistors being not completely turned off. The threshold voltage does not scale perfectly with Vcc.

Source-drain current increases exponentially with temperature, and thus dominates at high temperature, while gate leakage dominates at room temperature, but increases only slightly with temperature.

The I/O transistors must interface with legacy devices that operate on 3.3 V. Here we need thicker gate oxide, to withstand at least 3.6 V, preferably 4 V. (We managed to convince most customers that 5 V tolerance is no longer needed.) Most modern CMOS devices thus use two different gate oxide thicknesses, a thin oxide for the high-performance core of the chip (memory, microprocessor or FPGA) and a thicker oxide for the I/O transistors.

Virtex-4 and Virtex-5 go one step further and use a third thickness, called mid-ox since it is between the two established thicknesses. An FPGA always has many transistors that reside in the core logic, but they have no reason to be fast. Most obvious are the millions of transistors that store the configuration (six transistors for each configuration bit).

Giving these transistors a thicker gate oxide reduces their leakage current substantially.

That is why Xilinx uses “triple-oxide technology”, which we expect to become the standard for the industry.

随着工艺几何图形的缩小，晶体管变得更小、更便宜，栅极氧化物(将栅极与源极和漏极分开的二氧化硅层)必须变得更薄，以达到更高的开关速度。但是，薄的氧化物(低至16a = 1.6 nm)无法承受高于1.5 v的电压(过高的电压会随着时间的推移导致降解，尤其是在高温下，我们希望我们的电路至少在20年内保持在规格范围内)。

这就是为什么Vccint对Virtex-4降低到1.2 V，对Virtex-5设备降低到1.0 V。

薄层氧化物是高性能所必需的，也是低动态功耗的重要因素，但它也会导致泄漏电流急剧增加。漏电流有两个组成部分:栅漏电流只通过极薄的栅极氧化物，而源极漏电流则是由于晶体管没有完全关闭而引起的。阈值电压与Vcc的比例并不完全一致。

源极漏电流随温度呈指数增长，在高温下占主导地位，而栅极漏电流在室温下占主导地位，随温度仅略有增加。

I/O晶体管必须与运行在3.3 V的传统设备接口。在这里，我们需要更厚的栅极氧化物，至少能够承受3.6 V，最好是4v(我们设法说服了大多数客户，不再需要5v的公差)。因此，大多数现代CMOS器件使用两种不同的栅氧化层厚度，一种薄的氧化层用于高性能的芯片核心(存储器、微处理器或FPGA)，另一种厚的氧化层用于I/O晶体管。